1. Field of the Invention
The present invention relates to a semiconductor memory device and a computer, and in particular to a semiconductor memory device which produces a signal indicative of the fact that output is fixed in the operation of outputting stored data as well as a computer provided with this semiconductor memory device.
The semiconductor memory device according to the invention is applicable to any kinds of computer such as a super computer, a large scale computer, a work station and a personal computer.
2. Description of the Related Art
FIG. 1 shows a conventional semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In FIG. 1, an RAM (Random Access Memory) 1 receives address signals A0, A1, . . . as well as a control signal CTR which includes a row address strobe signal {overscore (RAS)}, a column address strobe signal {overscore (CAS)} and a write enable signal {overscore (WE)}, if it is a DRAM, or control signal CTR includes a chip select signal {overscore (CS)} and a write enable signal {overscore (WE)}, if it is an SRAM. In accordance with a state of control signal CTR, RAM 1 writes externally applied input data Din into memory cells selected by address signals A0, A1, . . . , or reads potentials corresponding data stored in memory cells selected by address signals A0, A1, . . . for externally applying the same as output data Dout.
A read operation of the conventional semiconductor memory device thus constructed will be described below with reference to timing charts of FIGS. 2 and 3. FIG. 2 is the timing chart showing the read operation in the case where RAM 1 is the SRAM. In the read operation, chip select signal {overscore (CS)} is set to the L-level as shown at (a) in FIG. 2 to activate the SRAM, and write enable signal {overscore (WE)} is set to the H-level as shown at (b) in FIG. 2. Externally applied address signals A0, A1, . . . change at time t0 as shown at (c) in FIG. 2.
In accordance with data stored in the memory cells selected by address signals A0, A1, . . . , output data Dout changes its state, as shown at (d) in FIG. 2, from a high impedance (Hi-Z) state to the H-level or L-level at time t1 when an address access time tAAC (e.g., 10 ns) elapses from the time to of change of address signals A0, A1, . . . When chip select signal {overscore (CS)} is set to the H-level at time t2 as shown at (a) in FIG. 2, the SRAM is deactivated, and output data Dout attains the high impedance (Hi-Z) state again as shown at (d) in FIG. 2.
FIG. 3 is the timing chart showing the read operation in the case where RAM 1 is the DRAM. Before time t0 at which row address strobe signal {overscore (RAS)} falls to the L-level as shown at (a) in FIG. 3, address signals A0, A1, . . . are set to the X-address of the memory cell to be selected as shown at (d) in FIG. 3. When row address strobe signal {overscore (RAS)} falls to the L-level at time t0 as shown at (a) in FIG. 3, the DRAM responding it takes in and latches the same using address signals A0, A1, . . . as the X-address. Then, write enable signal {overscore (WE)} is set to the H-level at time t1 as shown at (c) in FIG. 3, and the DRAM responds to the same and is controlled to perform the reading.
Column address strobe signal {overscore (CAS)} is raised to the L-level at time t3 as shown at (b) in FIG. 3. At time t2 preceding time t2, address signals A0, A1, . . . are set to the Y-address of the memory cell to be selected as shown at (d) in FIG. 3. Column address strobe signal {overscore (CAS)} falls to the L-level at time t3 as shown at (b) in FIG. 3. In accordance with data stored in the memory cell selected by the X-address and Y-address, output data Dout changes its state from the high impedance (Hi-Z) state to the H-level or L-level at time t4 after elapsing of an {overscore (RAS)} access time tRAS (e.g., 50 ns) from time to and hence after elapsing of a {overscore (CAS)} access time tCAS from time t3. When column address strobe signal {overscore (CAS)} is raised to the H-level at time t5 as shown at (b) in FIG. 3, output data Dout attains the high impedance (Hi-Z) state again as shown at (e) in FIG. 3.
In the conventional semiconductor memory device thus constructed, the specification of RAM prescribes the maximum access times (tAAC(max), tRAS(max), tCAS(max) and others) in connection with the access time. The specification also prescribes the operation conditions of RAM. For example, a prescribed power supply potential is 5Vxc2x110% (4.5 Vxe2x88x925.5 V), and a prescribed operation temperature is from 0xc2x0 C. to 70xc2x0 C.
The access time of RAM mainly depends on the performance of transistors forming the RAM. In general, a current drive capability of the MOS transistor decreases as the power supply potential decreases, and also decreases as the operation temperature decreases. The operation speed decreases as the current drive capability decreases. The maximum access time is equal to the access time required under the worst environmental conditions of RAM, i.e., at a low power supply potential in a high temperature.
When designing the timing of a system using a conventional RAM, the designed access time must be equal to the maximum access time in view of a margin for allowing use or operation under the worst conditions of a low power supply potential and a high temperature, even if the system will not be used under the worst conditions in practice. Therefore, in spite of the fact that the actual access time can be shorter than the maximum access time unless it is used under the worst conditions, the speed of the system is unduly low due to the timing margin determined in view of the use under the worst conditions.
In a system operating in synchronization with a clock of a fixed frequency, it is necessary to design the system to operate with a low frequency allowing correct operation of the RAM under the worst conditions of the system. In practice, the system may not be used under the worst conditions. Even in such a case that the system can be operated at a higher speed because, e.g., the RAM can be accessed at a higher speed, the system must actually operate at the low speed as if it were operating under the worst conditions due to the fact that the clock frequency is fixed, so that the system speed is unduly reduced.
Accordingly, it is an object of the invention to provide a semiconductor memory device which can perform a normal operation at an increased speed without changing a manufacturing process as well as a computer provided with the same.
Another object of the invention is to increase an operation speed of a semiconductor memory device and a computer by eliminating undue restriction relating to the operation speed of a system under conditions other than the worst conditions.
Still another object of the invention is to increase an operation speed of a semiconductor memory device and a computer by using data immediately when the data is supplied from the semiconductor memory device under conditions other than the worst conditions.
An additional object of the invention is to provide a semiconductor memory device and a computer allowing a faster operation by increasing a data output speed itself of the semiconductor memory device and by allowing immediate use of the data when the data is output.
A further additional object of the invention is to provide a semiconductor memory device and a computer which can coexist with a conventional system and can perform a conventional operation at a higher speed.
A computer according to the invention includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal applied through an address input terminal to a data output terminal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data to an output fixing signal output terminal; and a processing device operable to apply the address signal to the address input terminal, receive the data from the data output terminal, take in the data in response to the data output fixing signal attaining the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip.
When the storage device outputs the data, it also outputs the data output fixing signal at the predetermined level in response to the output of the data. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapsing of a maximum access time determined in a specification taking the worst conditions into consideration, so that the time can be effectively utilized and the data processing can be performed at a high speed. In the structure where the storage device and the processing device are formed on the single chip, data output fixing signal is used only on the chip, and external input/output of the signal into and from the chip can be performed by the same manner as the conventional system.
According to another aspect of the invention, a semiconductor memory device includes a plurality of memory cell arrays each including a plurality of sub-memory cell arrays each including a plurality of memory cells; a plurality of data output line pairs provided correspondingly to the plurality of sub-memory cell arrays and each receiving a potential corresponding to data stored in a selected memory cell among the plurality of memory cells contained in the corresponding sub-memory cell array; a plurality of differential amplifiers connected to the plurality of data output line pairs, respectively, and each amplifying a potential difference of the corresponding data output line pair to output two complementary amplified signals; an output circuit receiving the amplified signals from each of the differential amplifier circuit and outputting data corresponding to the amplified signals selected by an address signal to an output terminal corresponding to the amplified signals; a plurality of sub-output fixing signal generating circuits each outputting a sub-output fixing signal attaining a first predetermined level in response to the fact that one of the amplified signals supplied from the corresponding differential amplifier circuit attains the H-level and the other of the same attains the L-level; and an output fixing signal generating circuit connected to the plurality of sub-output fixing signal generating circuits and outputting a data output fixing signal to an output fixing signal output terminal in accordance with the plurality of sub-output fixing signals.
When the storage device outputs data formed of multiple bits, the storage device also outputs the data output fixing signal attaining the predetermined level in accordance with the fact that the multiple bit data is output onto the data output line pair. A processing device receiving the data from the storage device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, the data can be processed before elapsing of the maximum access time determined in the specification based on the assumptive worst conditions, so that the time can be effectively utilized and fast data processing is allowed.
According to still another aspect of the invention, a semiconductor memory device includes a memory cell array having a plurality of memory cells; a data output line pair receiving potentials being in a range from a first potential (e.g., ground potential) to a second potential (e.g., power supply potential) higher than the first potential and corresponding to data stored in the memory cell selected in accordance with an address signal from the plurality of memory cells in the memory cell array, and producing a potential difference between one of the potentials and the other of the same; a precharge device receiving a precharge signal to set the data output line pair to a precharge potential higher than the first potential and lower than the second potential in accordance with the precharge signal; a differential amplifier circuit receiving one and the other of the potentials of the data output line pair and amplifying signals on the data output line pair for outputting the amplified signals; and an output fixing signal generating circuit receiving the amplified signals from the differential amplifier circuit and outputting an output fixing signal attaining a predetermined level in response to the fact that one of the received signals attains the H-level and the other attains the L-level.
When the storage device outputs data formed of multiple bits, the storage device also outputs the data output fixing signal attaining the predetermined level in accordance with the fact the multiple bit data is output onto the data output line pair. A processing device receiving the data from the storage device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, the data can be processed before elapsing of the maximum access time determined in the specification based on the assumptive worst conditions, so that the time can be effectively utilized and fast data processing is allowed. Further, since the data output line pair is precharged to the potential between the first and second potentials prior to the output of the data, the potentials of the data output line pair are rapidly set to the potentials corresponding to the read data, so that data output can be rapidly performed.
According to yet another aspect of the invention, a computer includes a storage device having a plurality of memory cells, receiving a first signal indicative of existence and absence of request of operation and responding to predetermined change of the first signal indicative of generation of the request of the operation and an address signal by outputting a busy signal at a predetermined level, data from the memory cell corresponding to the address signal and a data output fixing signal attaining a predetermined level in accordance with the output of the data; and a processing device applying the address signal and an operation request signal indicative of the request of the operation to the storage device only when the busy signal is at a level other than the predetermined level, and taking in the data supplied from the storage device in accordance with the fact that the data output fixing signal supplied from the storage device attains the predetermined level for processing the same.
According to the above computer, when the storage device outputs the data, it also outputs the data output fixing signal attaining the predetermined level in response to the output of the data. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapsing of a maximum access time determined in a specification based on the assumptive worst conditions, so that the time can be effectively utilized and the data processing can be performed at a high speed. Upon receipt of the request of the operation, the storage device outputs the busy signal, so that it is also possible to use the processing device for suppressing the storage device from requesting the operation.
According to further another aspect of the invention, a semiconductor memory device includes a plurality of memory cells; and a device being responsive to a signal indicative of generation of request of operation and an address signal to output a busy signal at a predetermined level, data from the memory cell corresponding to the address signal and a data output fixing signal attaining a predetermined level in accordance with the fact that the data is output.
When the storage device outputs the data, it also outputs the data output fixing signal attaining the predetermined level in response to the output of the data. An external processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapsing of a maximum access time determined in a specification based on the assumptive worst conditions, so that the time can be effectively utilized and the data processing can be performed at a high speed. Upon receipt of the request of the operation, the storage device outputs the busy signal, so that it is also possible to use the processing device for suppressing the storage device from requesting the operation.
According to an additional aspect of the invention, a semiconductor memory device includes a main memory having a plurality of DRAM memory cells, and receiving a main memory address signal to output data stored in the DRAM memory cell selected by the main memory address signal and a main memory output fixing signal attaining a first predetermined level in response to the output of the data; and a cache memory. The cache memory includes an SRAM memory array and a tag memory array. The SRAM memory array includes a plurality of SRAM memory cells, and receives a cache memory address signal to output the data stored in the SRAM memory cell selected in accordance with the cache memory address signal and output a cache memory output fixing signal attaining a second predetermined level in response to the output of the data. The tag memory array includes a plurality of SRAM memory cells, and receives the cache memory address signal to output tag address data stored in the SRAM memory cell selected in accordance with the cache memory address signal. The semiconductor memory device further includes a comparator circuit receiving a portion of the main memory address signal corresponding to the tag address data and the tag address data, and outputting a cache-hit signal attaining a first level or a second level depending on whether they agree or not; and a select circuit receiving the data and the cache memory output fixing signal from the cache memory and receiving the cache-hit signal sent from the comparator circuit to select, depending on the cache-hit signal, the data and the cache memory data output fixing signal sent from the cache memory, or the data and the main memory data output fixing signal sent from the main memory for outputting the same as output data and an output fixing signal.
When the storage device outputs the data, it also outputs the data output fixing signal attaining the predetermined level in response to the output of the data. A processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapsing of a maximum access time determined in a specification based on the assumptive worst conditions, so that the time can be effectively utilized and the data processing can be performed at a high speed. Further, the device can generate the output fixing signal indicative of the facts that the data is output from the cache memory, if the read data is on the cache memory, and that the data is output from the main memory, if the read data is on the main memory. Accordingly, an operation speed of the storage system including the cache memory can be further increased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.